1 jun-29-2004 dual n-channel enhancement mode field effect transistor P07D03LVG sop-8 lead-free niko-sem absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol limits units drain-source voltage v ds 30 v gate-source voltage v gs 20 v t c = 25 c 7 continuous drain current t c = 70 c i d 6 pulsed drain current 1 i dm 40 a t c = 25 c 2 power dissipation t c = 70 c p d 1.3 w junction & storage temperature range t j , t stg -55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-ambient r ja 62.5 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1 % electrical characteristics (t c = 25 c, unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain-source breakdown voltage v (br)dss v gs = 0v, i d = 250 a 30 gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.7 1 1.4 v gate-body leakage i gss v ds = 0v, v gs = 20v 100 na v ds = 24v, v gs = 0v 1 zero gate voltage drain current i dss v ds = 20v, v gs = 0v, t j = 55 c 10 a on-state drain current 1 i d(on) v ds = 5v, v gs = 10v 25 a g : gate d : drain s : source product summary v (br)dss r ds(on) i d 30 20m [ 7a
2 jun-29-2004 dual n-channel enhancement mode field effect transistor P07D03LVG sop-8 lead-free niko-sem v gs = 2.5v, i d = 5a 40 48 drain-source on-state resistance 1 r ds(on) v gs = 4.5v, i d = 6a 23 30 m [ v gs = 10v, i d = 7a 18 25 forward transconductance 1 g fs v ds = 15v, i d = 5a 16 s dynamic input capacitance c iss 830 output capacitance c oss 185 reverse transfer capacitance c rss v gs = 0v, v ds = 15v, f = 1mhz 80 pf total gate charge 2 q g 9 13 gate-source charge 2 q gs 2.8 gate-drain charge 2 q gd v ds = 0.5v (br)dss , v gs = 5v, i d = 7a 3.1 nc turn-on delay time 2 t d(on) 5.7 rise time 2 t r v ds = 15v 10 turn-off delay time 2 t d(off) i d ? 1a, v gs = 10v, r gen = 6 [ 18 fall time 2 t f 5 ns source-drain diode ratings and characteristics (t c = 25 c) continuous current i s 3 pulsed current 3 i sm 6 a forward voltage 1 v sd i f = 1a, v gs = 0v 1 v reverse recovery time t rr i f = 5a, dl f /dt = 100a / s 15.5 ns reverse recovery charge q rr 7.9 nc 1 pulse test : pulse width 300 sec, duty cycle 2%. 2 independent of operating temperature. 3 pulse width limited by maximum junction temperature. remark: the product marked with ?p 07d03lvg?, date code or lot # orders for parts with lead-free plating can be placed using the pxxxxxxxg parts name
3 jun-29-2004 dual n-channel enhancement mode field effect transistor P07D03LVG sop-8 lead-free niko-sem typical performance characteristics
4 jun-29-2004 dual n-channel enhancement mode field effect transistor P07D03LVG sop-8 lead-free niko-sem
5 jun-29-2004 dual n-channel enhancement mode field effect transistor P07D03LVG sop-8 lead-free niko-sem soic-8(d) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 4.8 4.9 5.0 h 0.5 0.715 0.83 b 3.8 3.9 4.0 i 0.18 0.254 0.25 c 5.8 6.0 6.2 j 0.22 d 0.38 0.445 0.51 k 0 4 8 e 1.27 l f 1.35 1.55 1.75 m g 0.1 0.175 0.25 n h c b a d e f g i j k
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